1. Field of the Invention
The present invention relates to a semiconductor device having a TEG (Test Element Group), a semiconductor device manufacturing method, and a semiconductor device test method.
2. Description of the Related Art
A TEG (Test Element Group) chip obtained by forming the building components (interconnection, transistor, capacitor, resistor, and the like) of a semiconductor device on a chip has conventionally been used to facilitate the reliability evaluation of the semiconductor device or the like.
In a conventional TEG chip 10, as shown in FIGS. 13 and 14, a test site (test area) portion 20 and probe pad portion 30 are formed on one silicon substrate 70.
The test site portion 20 is a region where a test element 22 such as a transistor or capacitor exists. The probe pad portion 30 is a region where a probe pad for arranging a probe exists.
In the conventional TEG chip 10, one TEG 11 is constituted by, e.g., the test site portion 20 of three test elements 22 and 16 probe pads 37. More specifically, the three test elements 22 are arranged at the center of the TEG 11, and eight probe pads 37 are arranged on each of two sides along the test elements 22. Each probe pad 37 is electrically connected to the test element 22 via interconnections and contacts in insulating films 71, 72, 73, 74, 75, and 76.
In this situation, the integration degree of semiconductor integrated circuits is increasing year by year. Semiconductor devices to be evaluated at the test site have been downsized. However, probe pads for electrically evaluating a test site are still large despite such reduction in the feature size of semiconductor devices.
For example, in the 0.11-μm generation, the probe pad size is 80 μm□ to 100 μm□, and the test site is laid out in almost the same area as the area occupied by the probe pad. Hence, the measurement probe pad occupies 60% of the TEG chip at maximum in the TEG layout. Note that the probe pad means one arranged for only a probe.
In the prior art, it is difficult to reduce the probe pad area because the probe pad cannot be shared between a plurality of test elements and the test site is evaluated by a common probe card.
As described above, in the prior art, the area occupied by the probe pad in the TEG chip is large, and it is difficult to reduce the probe pad area. The region where the test site can be formed is small, and the test site region is limited by the probe pad area.